MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2251

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
ADC_SAMPLE_
ADC_SAMPLE_
ADC_SAMPLE_
ADC_SAMPLE_
SOFTWARE_
HALFWORD_
SHIFT_BITS_
PRECISION
TRIGGER
DISCARD
RSRVD1
ENDIAN
26 21
20 19
18 17
SWAP
14 12
NUM
Field
27
16
15
11: no trigger.
When set to 1'b1,trigger the ADC to start the conversion.This bit can be auto cleared.
Reserved.
This bit field specifies the number of samples to be discarded whenever the analog ADC is firstly powered
up.Take effect when hsadc_run is asserted.
00= discard first sample
01= discard first 2 samples
10= discard first 3 samples
11= discard first 4 samples
1_SAMPLE = 0x0 discard first sample before first capture.
2_SAMPLES = 0x1 discard 2 samples before first capture.
3_SAMPLES = 0x2 discard 3 samples before first capture.
4_SAMPLES = 0x3 discard 4 samples before first capture.
This bit field specifies the precision of sample data.Take effect when hsadc_run is asserted.
00= When set to 2'b00,the HSADC output 8-bits sample data.
01= When set to 2'b01,the HSADC output 10-bits sample data.
10= When set to 2'b10,the HSADC output 12-bits sample data.
11= When set to 2'b11,no data output.
This bit field specifies the endian of sample data.Take effect when hsadc_run is asserted.
0= When set to 1'b0,the HSADC outputs little endian sample data.
1= When set to 1'b1,the HSADC outputs big endian sample data.
This bit field specifies whether to do halfword swap on the sample data.Take effect when hsadc_run is
asserted.
0= When set to 1'b0,the HSADC don't swap the output sample data.
1= When set to 1'b1,the HSADC do 16-bits swap on the output sample data.
This bit field specifies the bits number of sample data to be left shifted.Take effect when hsadc_run is
asserted.
000= When set to 3'b000,the sample data remains unchanged.
001= When set to 3'b001,the sample data be left shifted 1 bit.
010= When set to 3'b010,the sample data be left shifted 2 bit.
011= When set to 3'b011,the sample data be left shifted 3 bit.
100= When set to 3'b100,the sample data be left shifted 4 bit.
When set to other value,the sample data remains unchanged.
For 8-bits mode,all these setting are valid.For 10-bits,only 3'b000,3'b001,3'b010 are valid.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_HSADC_CTRL0 field descriptions (continued)
Description
Chapter 37 High-Speed ADC (HSADC)
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