MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2257

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
HW_HSADC_SEQUENCE_NUM_CLR: 0x048
HW_HSADC_SEQUENCE_NUM_TOG: 0x04C
This register specifies the number of sequences.
EXAMPLE
Address:
Re-
37.5.6 HSADC FIFO Data Register (HW_HSADC_FIFO_DATA)
The HSADC FIFO Data Register is for the DMA or host CPU to read data from the FIFO
by APB bus.
This register contains the programming paramters for multi-chip attachment mode, clock
divider value, active high, low values and period for channel 1.
EXAMPLE
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
HW_HSADC_SEQUENCE_NUM_WR(0x0000001f);
HW_HSADC_FIFO_DATA_RD();
R
R
SEQUENCE_
31
31
0
0
NUM
Field
31 0
30
30
0
0
29
29
0
0
HW_HSADC_SEQUENCE_NUM 8000_2000h base + 40h offset = 8000_2040h
HW_HSADC_FIFO_DATA
28
28
0
0
Number of sequence. 0 means infinite sequences. Note that when set to 0,the ADC can only be stopped
by software disabling.Take effect when hsadc_run is asserted.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
HW_HSADC_SEQUENCE_NUM field descriptions
0
24
24
0
0
23
23
0
0
22
22
0
0
21
21
0
0
8000_2000h base + 50h offset = 8000_2050h
20
20
0
0
19
19
0
0
18
18
0
0
SEQUENCE_NUM
17
17
0
0
FIFO_DATA
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
Chapter 37 High-Speed ADC (HSADC)
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
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0
0
0
0

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