MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 346

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

APBH DMA
A single command structure can issue 32-bit PIO write operations to key registers in the
associated device using the same APB bus and the controls, it uses to write DMA data bytes
to the device. For example, this allows a chain of operations to be issued to the GPMI
controller to send NAND command bytes, address bytes, and data transfers where the
command and the address structure is completely under software control, but the
administration of that transfer is handled autonomously by the DMA. Each DMA structure
can have 0–15 PIO words appended to it. The #PIOWORDs field, if non-zero, instructs the
DMA engine to copy these words to the APB, beginning at PADDR = 0x0000 and
incrementing its PADDR for each cycle.
The DMA master generates only normal read/write transfers to the APBH. It does not
generate set, clear, or toggle (SCT) transfers.
After any requested PIO words have been transferred to the peripheral, the DMA examines
the two-bit command field in the channel command structure.
Command chains are built up using the general structure, as shown in the figure.
The following table shows the four commands implemented by the DMA.
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DMA COMMAND
00
01
10
Figure 6-2. AHB-to-APBH Bridge DMA Channel Command Structure
NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA
transfer.
DMA_WRITE. Perform any requested PIO word transfers, then perform a DMA transfer from the peripheral
for the specified number of bytes.
DMA_READ. Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral
for the specified number of bytes.
USAGE
word 3-n
word 0
word 1
word 2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 6-2. APBH DMA Commands
XFER_COUNT
BUFFER ADDRESS
NEXTCMDADDR
PIOWORD
Freescale Semiconductor, Inc.