MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 488
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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Programmable Registers
6.5.112 AHB to APBH DMA channel 14 Debug Information
This register gives debug visibility for the APB and AHB byte counts for DMA channel
14.
Because channel 14 is not assigned to any peripheral, this register is of no practical usage
and just reserved for compatibility.
Address:
Re-
6.5.113 APBH DMA channel 15 Current Command Address Register
The APBH DMA channel 15 current command address register points to the multiword
command that is currently being executed. Commands are threaded on the command address.
488
set
Bit
W
R
AHB_BYTES
APB_BYTES
31
0
31 16
Field
15 0
30
0
Field
29
0
HW_APBH_CH14_DEBUG2
(HW_APBH_CH14_DEBUG2)
(HW_APBH_CH15_CURCMDAR)
28
0
This value reflects the current number of APB bytes remaining to be transfered in the current transfer.
This value reflects the current number of AHB bytes remaining to be transfered in the current transfer.
27
0
HW_APBH_CH14_DEBUG1 field descriptions (continued)
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
APB_BYTES
0
0x1C
0x1D
0x1E
0x1F
HW_APBH_CH14_DEBUG2 field descriptions
24
0
WRITE_WAIT — During DMA Write transfers, the state machine waits in this state until the
AHB master completes the write to the AHB memory space.
HALT_AFTER_TERM — If HALTONTERMINATE is set and a terminate signal is set, the
state machine enters this state and effectively halts. A channel reset is required to exit this
state
CHECK_WAIT — If the Chain bit is a 0, the state machine enters this state and effectively
halts.
WAIT_READY — When the NAND Wait for Ready bit is set, the state machine enters this
state until the GPMI device indicates that the external device is ready.
23
0
22
0
21
0
8000_4000h base + 780h offset = 8000_4780h
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
Description
13
0
12
0
11
0
10
0
AHB_BYTES
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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