MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1818

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Ipv4 and Ipv6 Priority Look Up
The table is implemented in a single 320 deep table which is used for both IPv4 6-bit TOS
and IPv6 8-bit COS mappings.
To write a table row into the table the address is provided in bits 8:0 and the data in bits
13:9, where bit 9 represents bit0 of the data and bit13 represents bit5 of the data.
To read a table row, the read bit must be set when writing into the IP_PRIORITY register.
This will trigger a read transaction to the address provided in bits 8:0 of the register. After
this, reading the register provides the data returned from the table for this address.
When writing an entry into the table, software can only write the mapping for all ports in
one write transaction. Therefore software must implement a read-modify-write scheme, to
first read the current table contents, modify the priority bits for the port of interest without
modifying the other ports bits and then write back the complete data word into the table.
29.4.6.4 Priority Resolution
The Priority Resolution function, for a Port n, is, on each port independently, programmable
with the registers to enable or disable VLAN or IP or MAC address based classification.
The priority resolution follows the following ruleset depending on which classifications are
enabled (PRIORITY_CFGn) and which fields are found within the frame:
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• The first 256 entries represent the IPv6 COS field mapping. The received COS field of
• The last 64 entries represent the IPv4 DiffServ field mapping. The received DiffServ
• Each entry of the table provides the priority mapping for port0 in bits 1:0 (00=queue0,
• if IP classification is enabled and IP header found => map priority according
a frame is used to address a row from 0..255. The value stored is read and used as
priority for the frame.
(upper 6-bits of TOS) value of a frame is used to address a row from 256..319.
01=queue1, 10=queue2, 11=queue3), for port 1 in bits 3:2 and port 2 in bits 5:4.
IP_PRIORITY table
Figure 29-7. IP_PRIORITY Mapping Table Programming Model
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
31
31: read transaction
per port data
9 8
per port data
address
8:0
0
address
bit 5..
5:4 3:2 1:0
0
256..319..IPv4 TOS
mapping
0..255: IPv6 COS
mapping
Freescale Semiconductor, Inc.