MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1112

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
14.8.2 AXI Monitor Control (HW_DRAM_CTL01)
This is a DRAM configuration register.
1112
Reset
Reset
BRESP_TIMING
CKE_SELECT
USER_DEF_
SREFRESH_
Bit
Bit
REG_0_1
W
W
R
R
ENTER
Field
31 3
2
1
0
31
15
0
0
HW_DRAM_CTL00
30
14
0
0
User-defined output register 0.
Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges
from 0 to 7)
This bit selects which output logic drives the CKE pin.
This is required since the initial state of CKE is low for DDR2 and high for LPDDR.
This bit MUST be set appropriately before (NOT concurrently) the EMI clock is enabled by setting field
EMI_CLK_DLL_ENABLE.
0x0
0x1
Initiates a self-refresh to the DRAMs. This pin updates the srefresh parameter.
This bit changes when the BRESP is issued over the AXI bus interface for bufferable AXI write transactions.
0x0
0x1
29
13
0
0
DDR2 — CKE will be low before the EMI clock is enabled and the initialization sequence commences.
LPDDR — CKE will be high before the EMI clock is enabled and the initialization sequence commences.
BUFFERABLE — BRESP is returned when command and data are received by the AXI port.
SEMI_BUFFERABLE — BRESP is returned when command is accepted into the internal EMI
command queue.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
800E_0000h base + 0h offset = 800E_0000h
HW_DRAM_CTL00 field descriptions
27
11
0
0
USER_DEF_REG_0_1[15:3]
26
10
0
0
USER_DEF_REG_0_1[31:16]
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0