MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2047

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

32.4.5 USB PHY Status Register (HW_USBPHY_STATUS)
The USB PHY Status Register holds results of IRQ and other detects.
Address:
Freescale Semiconductor, Inc.
Reset
HOSTDISCONDETECT_IRQ
ENHOSTDISCONDETECT
DEVPLUGIN_POLARITY
ENDEVPLUGINDETECT
ENIRQHOSTDISCON
Bit
W
R
ENOTGIDDETECT
31
0
RSVD1
RSVD0
Field
7
6
5
4
3
2
1
0
HW_USBPHY_STATUS
30
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBPHY_CTRL field descriptions (continued)
Enables circuit to detect resistance of MiniAB ID pin.
Reserved.
For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in. If
set to 1, then it trips the interrupt if the device is unplugged.
For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
Indicates that the device has disconnected in high-speed mode. Reset this bit by writing a 1 to
the SCT clear address space and not by a general write.
Enables interrupt for detection of disconnection to Device when in high-speed host mode. This
should be enabled after ENDEVPLUGINDETECT is enabled.
For host mode, enables high-speed disconnect detector. This signal allows the override of
enabling the detection that is normally done in the UTMI controller. The UTMI controller enables
this circuit whenever the host sends a start-of-frame packet.
Reserved.
28
0
27
0
8007_C000h base + 40h offset = 8007_C040h
26
0
25
0
RSVD4[31:16]
24
0
23
0
Description
22
0
21
0
Chapter 32 Integrated USB 2.0 PHY
20
0
19
0
18
0
17
0
2047
16
0