MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1054

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
13.3.29 DCP Channel 3 Semaphore Register (HW_DCP_CH3SEMA)
The DCP Channel 3 semaphore register is used to synchronize the CPU instruction stream
and the DMA chain processing state. After a command chain has been generated in memory,
software should write the address of the first command descriptor to the CMDPTR register
and then write a non-zero value to the semaphore register to indicate that the channel is
active. Each command packet has a chaining bit which indicates that another descriptor
should be loaded into the channel upon completion of the current descriptor. If the chaining
bit is not set, the next address will not be loaded into the CMDPTR register. Each packet
also contains a decrement semaphore bit, which indicates that the counting semaphore
should be decremented after the operation. A channel is considered active when the
semaphore is a non-zero value. When programming a series operations, software must
properly program the semaphore values in conjunction with the decrement_semaphore bits
in the control packets to ensure that the proper number of descriptors are activated. A
semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR
register. The logic will also clear the semaphore if an error has occurred.
Each DCP channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DCP chain processing. DCP processing continues until the
engine attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DCP channel is stalled until software increments the semaphore
count.
Address:
Re-
1054
set
Bit
W
R
INCREMENT
31
0
RSVD2
RSVD1
VALUE
31 24
23 16
Field
15 8
7 0
30
0
29
0
HW_DCP_CH3SEMA
RSVD2
28
0
Reserved, always set to zero.
This read-only field shows the current (instantaneous) value of the semaphore counter.
Reserved, always set to zero.
The value written to this field is added to the semaphore count in an atomic way such that simultaneous
software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads
back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP
channel decrements the count on the same clock, then the count is incremented by a net one.The semaphore
may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
HW_DCP_CH3SEMA field descriptions
0
22
0
8002_8000h base + 1D0h offset = 8002_81D0h
21
0
VALUE
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
RSVD1
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
INCREMENT
0
5
0
4
3
0
0
2
0
1
0
0