MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 605

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.5.86 APBX DMA Channel 11 Buffer Address Register
The APBX DMA Channel 11 buffer address register contains a pointer to the data buffer
for the transfer. For immediate forms, the data is taken from this register. This is a byte
address which means transfers can start on any byte boundary.
This register holds a pointer to the data buffer in system memory. After the command values
have been read into the DMA controller and the device controlled by this channel, then the
DMA transfer will begin, to or from the buffer pointed to by this register.
Address:
Re-
7.5.87 APBX DMA Channel 11 Semaphore Register
The APBX DMA Channel 11 semaphore register is used to synchronize between the CPU
instruction stream and the DMA chain processing state.
Each DMA channel has an 8 bit counting semaphore used to synchronize between the
program stream and the DMA chain processing. DMA processing continues until the DMA
attempts to decrement a semaphore which has already reached a value of zero. When the
attempt is made, the DMA channel is stalled until software increments the semaphore count.
Freescale Semiconductor, Inc.
set
Bit
W
R
ADDRESS
31
0
Field
31 0
Field
30
0
29
0
(HW_APBX_CH11_BAR)
(HW_APBX_CH11_SEMA)
HW_APBX_CH11_BAR
28
0
Address of system memory buffer to be read or written over the AHB bus.
27
0x1
0x2
0
26
0
HW_APBX_CH11_CMD field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer from
the peripheral for the specified number of bytes.
DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer to the
peripheral for the specified number of bytes.
25
0
24
0
HW_APBX_CH11_BAR field descriptions
23
0
22
0
8002_4000h base + 600h offset = 8002_4600h
21
0
20
0
19
0
18
0
17
0
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
ADDRESS
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
605
0
0