MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2080

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Behavior During Reset
33.3 Behavior During Reset
HCLK and CLK_DIS_LCDIF must be running before making any changes to SFTRST or
CLKGATE bits. A soft reset (SFTRST) can take multiple clock periods to complete, so do
NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically.
See the section
SFTRST and CLKGATE bit fields.
33.4 Programmable Registers
LCDIF Hardware Register Format Summary
2080
8003_0000
8003_0010
8003_0020
8003_0030
8003_0040
8003_0050
8003_0060
Absolute
address
(hex)
LCD_VSYNC
LCD_RESET
LCD_BUSY /
PIN NAME
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCDIF General Control Register (HW_LCDIF_CTRL)
LCDIF General Control1 Register (HW_LCDIF_CTRL1)
LCDIF General Control2 Register (HW_LCDIF_CTRL2)
LCDIF Horizontal and Vertical Valid Data Count Register
(HW_LCDIF_TRANSFER_COUNT)
LCD Interface Current Buffer Address Register
(HW_LCDIF_CUR_BUF)
LCD Interface Next Buffer Address Register
(HW_LCDIF_NEXT_BUF)
LCD Interface Timing Register (HW_LCDIF_TIMING)
Correct Way to Soft Reset a Block
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
8-bit DOTCLK
LCD_VSYNC)
LCD_RESET
(OR optional
LCD_BUSY
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD IF
Register name
HW_LCDIF memory map
16-bit DOTCLK
LCD_VSYNC)
LCD_RESET
(OR optional
LCD_BUSY
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD IF
18-bit DOTCLK
LCD_VSYNC)
LCD_RESET
(OR optional
LCD_BUSY
for additional information on using the
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD IF
(in bits)
Width
32
32
32
32
32
32
32
24-bit DOTCLK
Access
LCD_VSYNC)
LCD_RESET
(OR optional
LCD_BUSY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD IF
Freescale Semiconductor, Inc.
C000_0000h
Reset value
000F_0000h
0020_0000h
0001_0000h
0000_0000h
0000_0000h
0000_0000h
8-bit DVI
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD IF
33.4.1/2082
33.4.2/2085
33.4.3/2088
33.4.4/2090
33.4.5/2091
33.4.6/2091
33.4.7/2092
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