MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1013

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 13 Data Co-Processor (DCP)
If the ENABLE_CIPHER bit is set, the data is encrypted or decrypted based on the
CIPHER_ENCRYPT bit using the key/encryption settings from the Control1 field. The
OTP_KEY and PAYLOAD_KEY indicates the source of the keys for the operation. If the
OTP_KEY value is set, the KEY_SELECT field from the Control1 register indicates which
OTP key is to be used. If the PAYLOAD_KEY bit is set, the first entry in the payload is
the key to be used for the operation. If neither bit is set, the KEY_SELECT field indicates
an index in the key RAM that contains the key to be used. (For cases when both the
OTP_KEY and PAYLOAD_KEY bits are set, the PAYLOAD_KEY takes precedence.)
The HASH_ENABLE enables hashing of the data with the HASH_OUTPUT bit controlling
whether the input data (HASH_OUTPUT=0) or output data (HASH_OUTPUT=1) is hashed.
In addition, the hardware can be programmed to automatically check the hashed data if the
HASH_CHECK bit is set. If the hash does not match, an interrupt is generated and the
channel terminates operation on the current chain. The hashing algorithms also require two
additional fields in order to operate properly. The HASH_INIT bit should be set for the first
block in a hashing pass to properly initialize the hashing function. The HASH_TERM bit
must be set on the final block of a hash to notify the hardware that the hashing operation is
complete so that it can properly pad the tail of the buffer according to the hashing algorithm.
This flag also triggers the write-back of the hash output to the work packet's payload area.
The CONSTANT_FILL flag may be used for both memcopy and blit operations. When this
is set, the source address field is used instead as a constant that is written to all locations in
the output buffer.
The WORDSWAP and BYTESWAP bits enable muxes around the FIFO to swap data to
handle little-endian and big-endian storage of data in system memory. When these bits are
cleared, data is assumed to be in little-endian format. When all bits are set, data is assumed
to be in big-endian format.
The TAG field is used to identify the work packet and the associated completion status. As
each packet is completed, the channel provides the status and tag information of the last
packet processed.
13.2.6.4.3 Control1 Field
The Control1 field (shown in the following table) provides additional values used when
hashing or encrypting/decrypting data. For blit operations, this field indicates the number
of bytes in a frame buffer line, which is used to calculate the address for successive lines
in each blit operation.
Table 13-6. DCP Control1 Field
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1013