MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2054
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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Programmable Registers
2054
EN_USB_CLKS
PLL_LOCKED
TSTI_TX_DM
PLL_POWER
TESTMODE
ANALOG_
RSVD0
Field
15 3
17
16
2
1
0
Analog testmode bit. Drives value on the DM pad. Default value is 1'b0. This bit came from the test control
module.
Analog testmode bit. Set to 0 for normal operation. Set to 1 for engineering debug of analog PHY block.
This bit came from the test control module.
Reserved.
If set to 0, 9-phase PLL outputs for USB PHY are powered down. If set to 1, 9-phase PLL outputs for USB
PHY are powered up. Additionally, the UTMICLK120_GATE and UTMICLK30_GATE must be deasserted
in the UTMI phy to enable USB operation. This bit came from the clkctrl PIO control block
(clkctrl_pllctrl0_en_usb_clks).
Software controlled bit to indicate when the USB PLL has locked. Software needs to wait 10 us after enabling
the PLL POWER bit (0) before asserting this bit. If set to 0, tells the UTMI module that the USB PLL has not
locked. If set to 1, tells the UTMI module that the USB PLL has locked. Software should clear this bit prior
to turning off the USB PLL. This bit came from the clkctrl module.
USB PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL on before using the PLL
as a clock source. This is the time the PLL takes to lock to 480 MHz. This bit came from the clkctrl PIO
control block (clkctrl_pllctrl0_power).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBPHY_IP field descriptions (continued)
Description
Freescale Semiconductor, Inc.
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