MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 864

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
864
Reset
BUSY_REF_CPU
INTERRUPT_
BUSY_REF_
DIV_XTAL_
DIV_CPU_
FRAC_EN
DIV_XTAL
FRAC_EN
Bit
DIV_CPU
W
RSRVD5
RSRVD4
RSRVD3
RSRVD2
RSRVD1
R
31 30
25 16
15 13
XTAL
WAIT
Field
9 6
5 0
29
28
27
26
12
11
10
15
0
RSRVD3
14
0
Always set to zero (0).
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
Always set to zero (0).
1 = Enable fractional divide. 0 = Enable integer divide.
This field controls the divider connected to the crystal reference clock that drives the CLK_P domain when
bypass is selected.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
Always set to zero (0).
Gate off CLK_P while waiting for an interrupt.
Always set to zero (0).
Reserved - Always set to zero (0).
Always set to zero (0).
This field controls the divider connected to the ref_cpu reference clock that drives the CLK_P domain when
bypass is NOT selected. For changes to this field to take effect, the ref_cpu reference clock must be running.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_CLKCTRL_CPU field descriptions
11
0
10
0
0
9
RSRVD1
0
8
Description
0
7
0
6
5
0
4
0
Freescale Semiconductor, Inc.
DIV_CPU
0
3
0
2
0
1
1
0