MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1644

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

IEEE 1588 Functions
26.3.13.4 Transmit Timestamping
On transmit, only 1588 event frames need to be time-stamped. The Client application (for
example, the MAC driver) should detect 1588 event frames and set 'TS' bit in
Enhanced
uDMA Transmit Buffer
Descriptor.
For every transmitted frame, the MAC returns the captured timestamp in '1588 Timestamp'
and the transmit status TSE in
Enhanced uDMA Transmit Buffer
Descriptor. The transmit
status bit indicates that the application had the TS bit asserted for the frame.
If TS is set to '1', the MAC additionally memorizes the timestamp for the frame in the
register TS_TIMESTAMP. The interrupt bit EIR(TS_AVAIL) is set to indicate that a new
timestamp is available.
Software would implement a handshaking procedure by setting the TS bit when it transmits
the frame it needs a timestamp for and then waits on the EIR(TS_AVAIL) interrupt bit to
know when the timestamp is available. It then can read the timestamp from the
TS_TIMESTAMP register. This is done for all event frames, other frames will not use the
TS indicator and hence will not interfere with the timestamp capture.
26.3.13.5 Receive Timestamping
When a frame is received, the MAC latches the value of the timer when the frame SFD
field is detected and provides the captured timestamp '1588 Timestamp' in
Enhanced uDMA
Receive Buffer
Descriptor. This is done for all received frames.
The DMA controller has to ensure that it transfers the timestamp provided for the frame
into the corresponding field within the receive descriptor for software access.
26.3.13.6 Time Synchronization
To synchronize the local clock of a node to a remote master, the adjustable timer module
is available. It implements a free running 32-bit counter, which has an additional correction
counter connected to it. The correction counter is used to increase or decrease the rate of
the free running counter, enabling very fine granular changes of the timer for synchronization,
yet adding only very low jitter when performing corrections.
The application (software) implements, in a slave scenario, the required control algorithm
setting the correction to compensate for local oscillator drifts and locking the timer to the
remote master clock on the network.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1644
Freescale Semiconductor, Inc.