MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1286

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programming the BCH/GPMI Interfaces
reported in the status register. There is also a 16-bit HANDLE field in the
HW_GPMI_ECCCTRL register that is passed down the pipeline with each transaction.
This handle field can be used to speed firmware's detection of which transaction is being
reported.
These examples of reading and writing have focused on full page transfers of 4K page
NAND devices. Other device configurations can be specified by changing the ECCOUNT
field in the GPMI registers and reprogramming the BCH's HW_FLASHnLAYOUTm
registers.
The BCH and GPMI blocks are designed to be very efficient at reading single 512-byte
pages in one transaction. With no errors, the transaction takes less than 20 HCLKs longer
than the time to read the raw data from the NAND.
To summarize, the APBH DMA command chain for a BCH decode operation is shown in
Figure
16-10. Seven DMA command structures must be present for each NAND read
transaction decoded by the BCH. The seven DMA command structures for multiple NAND
read transaction blocks can be chained together to make larger units of work for the BCH,
and each will produce an appropriate error report in the BCH PIO space. Multiple NAND
devices can have such multiple chains scheduled. The results can come back out of order
with respect to the multiple chains.
16.4.3 Interrupts
There are two interrupt sources used in processing BCH protected NAND read and write
transfers. Since all BCH operations are initiated by GPMI DMA command structures, the
DMA completion interrupt for the GPMI is an important ISR. Both of the flow charts of
Figure 16-6
and
Figure 16-9
show the GPMI DMA complete ISR skeleton. In both reads
and writes, the GPMI DMA completion interrupt is used to schedule work INTO the error
correction pipeline. As the front end processing completes, the DMA interrupt is generated
and additional work, such as DMA chains, are passed to the GPMI DMA to keep it fed. For
write operations, this is the only interrupt that is generated for processing the NAND write
transfer.
For reads, however, two interrupts are needed. Every read is started by a GPMI DMA
command chain and the front end queue is fed as described above. The back end of the read
pipeline is drained by monitoring the BCH completion interrupt found int
HW_BCH_CTRL_COMPLETE_IRQ.
An BCH transaction consists of reading or writing all of the blocks requested in the
HW_GPMI_ECCCTRL_BUFFER_MASK bit field. As every read transaction completes,
it posts the status of all of the blocks to the HW_BCH_STATUS0 and HW_BCH_STATUS1
registers and sets the completion interrupt. The five stages of the BCH read pipeline
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1286
Freescale Semiconductor, Inc.