MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1252

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1252
Reset
DECOUPLE_CS
TIMEOUT_IRQ_
WRN_DLY_SEL
HALF_PERIOD
DLL_ENABLE
RDN_DELAY
BCH_MODE
GANGED_
RDYBUSY
Bit
W
R
RSVD2
RSVD1
31 25
23 22
15 12
Field
EN
24
21
20
19
18
17
16
15
0
RDN_DELAY
14
0
Always write zeroes to this bit field.
Decouple Chip Select from DMA Channel. Setting this bit to 1 will allow a DMA channel to specify any value
in the CTRL0_CS register field. Software can use one DMA channel to access all 8 Nand devices.
Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to match
the load on this pin.
0 = 4ns to 8ns; 1 = 6ns to 10ns; 2 = 7ns to 12ns; 3 = no delay.
Always write zeroes to this bit field.
Setting this bit to 1 will enable timeout IRQ for WAIT_FOR_READY commands in Nand mode. The
Device_Busy_Timeout value is used for this timeout.
Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0. This will
free up all, except one, RDY_BUSY input pins.
This bit selects which error correction unit will access GPMI. This bit must always be set to 1, since only the
BCH unit is available in this design.
Set this bit to 1 to enable the GPMI DLL. This is required for fast NAND reads (above 30MHz read strobe).
After setting this bit, wait 64 GPMI clock cycles for the DLL to lock before performing a NAND read.
Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation. DLL_ENABLE must
be zero while changing this field.
This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data
sampling.
The applied delay (AD) is between 0 and 1.875 times the reference period (RP). RP is one half of the GPMI
clock period if HALF_PERIOD=1
otherwise it is the full GPMI clock period. The equation is: AD = RDN_DELAY x 0.125 x RP. This value must
not exceed 16ns.
This variable is used to achieve faster NAND access. For example if the Read Strobe is asserted from time
0 to 13ns but the read access time is 20ns,
then choose AD=12ns will cause the data to be sampled at time 25ns (13+12) giving a 5ns data setup time.
If RP=13ns then RDN_DELAY = 12/(0.125 x 13ns)
= 7.38 (0111b). DLL_ENABLE must be zero while changing this field.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_GPMI_CTRL1 field descriptions
11
0
RSVD
10
0
0
9
0
8
Description
0
7
ABORT_WAIT_FOR_
READY_CHANNEL
0
6
5
0
4
0
Freescale Semiconductor, Inc.
0
3
1
2
RSVD0
0
1
0
0