MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1750

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Internal Interface Modes
11. Write the read address to the HW_I2C_DATA register.
12. Clear the HW_I2C_DEBUG0_DMAREQ bit.
13. Wait for the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit to assert.
14. Clear the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit.
15. Write the next HW_I2C_CTRL0 word.
16. Reassert the HW_I2C_CTRL0_RUN bit.
17. Wait for the HW_I2C_DEBUG0_ DMAREQ bit to assert.
18. Get the data from the interface by reading the HW_I2C_DATA register.
19. Clear the HW_I2C_DEBUG0_DMAREQ bit.
20. Continue steps 17 through 19 until all data is read and the HW_I2C_CTRL1_
DATA_ENGINE_CMPLT_IRQ bit asserts.
2
This basic way of handshaking with the I
C controller can be followed for reading or writing
2
any amount of data from any slave device on the I
C bus.
27.3.2 PIO Queue Mode
The PIO Queue mode is similar to the PIO mode described above except in this mode,
control and data writes are queued up into internal FIFOs and executed when the
HW_I2C_QUEUECTRL_QUEUE_RUN bit is set. There is one read and one write FIFO
implemented in the system. Each FIFO is eight words deep. This mode is enabled by setting
the HW_I2C_QUEUECTRL_PIO_QUEUE_MODE bit. This must be set before writing
any control/command words or data. To write control words, the information is written to
the HW_I2C_QUEUECMD register instead of the HW_I2C_CTRL register. This new
register is very similar to the HW_I2C_CTRL and has almost all the same fields except for
the soft reset and other block related fields. So essentially, the same control words in the
PIO mode example above can be used in this mode but need to be diverted to this new
control register. One difference from the other modes is that transfer data is written and
read using different registers. The HW_I2C_DATA register is still used similar to the other
2
modes but only for writing I
C transfer data. The HW_I2C_QUEUEDATA register is used
to read the receive transfer data is read from the block. As an example of how this mode
works, consider the PIO mode execution steps above. PIO Queue mode works the same
way with only slight differences. HW_I2C_QUEUECTRL_PIO_QUEUE_MODE bit must
be set before any other writes to the CTRL or DATA registers are executed. And instead
of kicking off a command and polling or waiting for an interrupt to sequence the writing
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1750
Freescale Semiconductor, Inc.