MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1340

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1340
RESP_ERR_IRQ
UNDERRUN_IRQ
UNDERRUN_EN
TIMEOUT_IRQ_
TIMEOUT_IRQ_
DATA_CRC_IRQ
TIMEOUT_IRQ
TIMEOUT_IRQ
TIMEOUT_IRQ
SDIO_IRQ_EN
RESP_ERR_
DATA_CRC_
SDIO_IRQ
IRQ_EN
IRQ_EN
RSVD2
RSVD1
RECV_
RESP_
RESP_
DATA_
DATA_
FIFO_
FIFO_
Field
EN
EN
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
If this is set, an SDIO card interrupt has occurred and an IRQ, if enabled, has been sent to the ICOLL. Write
a one to the SCT Clear address to reset this interrupt request status bit.
SDIO Card Interrupt IRQ Enable. 0: SDIO card IRQs masked. 1: SDIO card IRQs will be sent to the ICOLL.
When the CHECK_RESP bit in CTRL0 is set, if an unexpected response (or response CRC) is received
from the card, this bit will be set. Write a one to the SCT Clear address to reset this interrupt request status
bit.
SD/MMC Card Error IRQ Enable. 0: Card Error IRQ is Masked. 1: Card Error IRQ is enabled. When set to
1, if an SD/MMC card indicates a card error (bit is set in both the SD/MMC Error Mask and R1 Card Status
response), then a CPU IRQ will be asserted.
If this is set, a command response timeout has occurred, and an IRQ, if enabled, has been sent to the IRQ
Collector. This is used for SD/MMC response timeout. Write a one to the SCT Clear address to reset this
interrupt request status bit.
SD/MMC Card Command Respone Timeout Error IRQ Enable. 0: Response Timeout IRQ is Masked. 1:
Response Timeout IRQ is enabled. When set to 1, if an SD/MMC card does not respond to a command
within 64 cycles, then this CPU IRQ will be asserted.
Data Transmit/Receive Timeout Error IRQ. If the timeout counter expires before the DAT bus is ready for
write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Modes. Write a one to
the SCT Clear address to reset this interrupt request status bit.
Data Transmit/Receive Timeout Error IRQ Enable. If the timeout counter expires before the DAT bus is
ready for write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Modes.
Data Transmit/Receive CRC Error IRQ. Only valid for SD/MMC Modes. Write a one to the SCT Clear address
to reset this interrupt request status bit.
Data Transmit/Receive CRC Error IRQ Enable. Only valid for SD/MMC Modes.
FIFO Underrun Interrupt. If the FIFO is read when it is empty this bit will be set. Write a one to the SCT Clear
address to reset this interrupt request status bit.
FIFO Underrun IRQ Enable. If set and the FIFO_UNDERRUN_IRQ bit is asserted, an IRQ will be generated.
Reserved
Reserved
Data Timeout Interrupt. If enabled and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles
Pass before the DATA register is read. This is supported for SPI modes only (Modes 0,1,2). Write a one to
the SCT Clear address to reset this interrupt request status bit.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SSP_CTRL1 field descriptions
Description
Freescale Semiconductor, Inc.