MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1140

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
14.8.34 DRAM Control Register 36 (HW_DRAM_CTL36)
This is a DRAM configuration register.
Address:
1140
Reset
Reset
TREF_ENABLE
INITAREF
Bit
Bit
W
W
R
R
RSVD1
RSVD3
RSVD2
31 25
23 17
Field
Field
7 4
3 0
24
31
15
0
0
HW_DRAM_CTL36
30
14
0
0
'b1 = Do not issue any type of command during DLL initialization of the DRAM devices. If any other commands
are issued during the initialization time, they will be held off until DLL initialization is complete.
Always write zeroes to this field.
Number of auto-refresh cmds to execute during DRAM initialization.
Defines the number of auto-refresh commands needed by the DRAM devices to satisfy the initialization
sequence.
Always write zeroes to this field.
Issue auto-refresh cmds to the DRAMs every TREF cycles.
Enables refresh commands. If command refresh mode is configured, then refresh commands will be
automatically issued based on the tref parameter value and any refresh commands sent through the command
interface or the register interface. Refreshes will still occur even if the DRAM devices have been placed in
power down state by the assertion of the power_down parameter.
'b0 = Refresh commands disabled.
'b1 = Refresh commands enabled.
Always write zeroes to this field.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL35 field descriptions (continued)
RSVD3
OBSOLETE
28
12
0
0
800E_0000h base + 90h offset = 800E_0090h
HW_DRAM_CTL36 field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
Description
23
0
0
7
22
0
0
6
21
0
5
0
RSVD2
RSVD1
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0