MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1395

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

19.4.34 Debug Trap Range Low Address for AHB Layer 0
The Debug Trap Range Low Address Register defines the lower bound for an address range
that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs
within this range. This register applies only to AHB Layer 0.
This register sets the lower address that defines the debug trap function. When this function
is enabled, any active AHB cycle on Layer 0 which accesses this range will trigger an
interrupt to the ARM core.
EXAMPLE
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
TRAP_ENABLE
R
TRAP_L3_IRQ
TRAP_L0_IRQ
TRAP_IN_
31
0
RANGE
ADDR
Field
Field
31 0
30
3
2
1
0
0
29
0
HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW 8001_C000h base + 2C0h offset
= 8001_C2C0h
(HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW)
28
0
HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW field descriptions
0x3
0x4
0x5
This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and
the trap function is enabled with the TRAP_ENABLE bit.
This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and
the trap function is enabled with the TRAP_ENABLE bit.
Determines whether the debug trap function causes a match when the master address is inside (low-address
<= current-address <= high-address) the specified range.
0 = The trap occurs when the master address falls outside of the range.
1 = The check is inside the range.
Enables the AHB arbiter debug trap functions. When a trap occurs and this bit is set, an interrupt is sent to
the ARM core.
This field contains the 32-bit lower address for the debug trap range.
27
0
HW_DIGCTL_DEBUG_TRAP field descriptions (continued)
26
0
USB1 — USB1
ENET_M0 — ENET_M0
ENET_M1 — ENET_M1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
ADDR
16
0
15
0
Description
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1395
0
0