MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2319

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 39 Register Macro Usage
A CS operation does have one potential drawback. Whenever a field is modified, the
hardware sees a value of 0 before the final value is written. For most fields, passing through
the 0 state is not a problem. Nonetheless, this behavior is something to consider when using
a CS operation.
Also, a CS operation is not required for fields that are one bit wide. While the CS operation
works in this case, it is more efficient to simply set or clear the target bit (that is, one write
instead of two). A simple set or clear operation is also atomic, while a CS operation is not.
Note that not all macros for set, clear, or toggle (SCT) are atomic. For registers that do not
provide hardware support for this functionality, these macros are implemented as a sequence
of read/modify/write operations. When atomic operation is required, the developer should
pay attention to this detail, because unexpected behavior might result if an interrupt occurs
in the middle of the critical section comprising the update sequence.
39.3.1 Multi-Instance Blocks
Additionally, newer silicon architecture adds the concept of Multi-Instance Blocks which
is similar to Multi-Instance Registers, although a Multi-Instance Block may also contain
Multi-Instance Registers (There are none in the i.MX28). In order to accommodate that
(and additional chips going forward) Multi-Instance Blocks have a required additional
parameter specifying the block number but use otherwise identical nomenclature. This also
allows runtime usage of different blocks (perhaps unifying driver models) without
recompilation or near-duplication of code and run-time selection of macros.
The i.MX28 SOC starts all blocks from 1. Future chips will all start at index 0.
39.3.1.1 Examples
The SSP has two instances (numbered 1 and 2). To access the CTRL0 register in that block,
instead of having two separate include files with hard coded macros, one can use the
following:
HW_SSP_CTRL0_WR(instance, value);
where instance is 1 or 2, and value is (in this case) the 32 bit value to be written to the
SSP_CTRL0 register in the block specified by instance.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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