MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2081

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
8003_00C0
8003_00D0
8003_01C0
8003_0070
8003_0080
8003_0090
8003_00A0
8003_00B0
8003_00E0
8003_00F0
8003_0100
8003_0110
8003_0120
8003_0130
8003_0140
8003_0150
8003_0160
8003_0170
8003_0180
8003_0190
8003_01A0
8003_01B0
Absolute
address
(hex)
LCDIF VSYNC Mode and Dotclk Mode Control Register0
(HW_LCDIF_VDCTRL0)
LCDIF VSYNC Mode and Dotclk Mode Control Register1
(HW_LCDIF_VDCTRL1)
LCDIF VSYNC Mode and Dotclk Mode Control Register2
(HW_LCDIF_VDCTRL2)
LCDIF VSYNC Mode and Dotclk Mode Control Register3
(HW_LCDIF_VDCTRL3)
LCDIF VSYNC Mode and Dotclk Mode Control Register4
(HW_LCDIF_VDCTRL4)
Digital Video Interface Control0 Register
(HW_LCDIF_DVICTRL0)
Digital Video Interface Control1 Register
(HW_LCDIF_DVICTRL1)
Digital Video Interface Control2 Register
(HW_LCDIF_DVICTRL2)
Digital Video Interface Control3 Register
(HW_LCDIF_DVICTRL3)
Digital Video Interface Control4 Register
(HW_LCDIF_DVICTRL4)
RGB to YCbCr 4:2:2 CSC Coefficient0 Register
(HW_LCDIF_CSC_COEFF0)
RGB to YCbCr 4:2:2 CSC Coefficient1 Register
(HW_LCDIF_CSC_COEFF1)
RGB to YCbCr 4:2:2 CSC Coefficent2 Register
(HW_LCDIF_CSC_COEFF2)
RGB to YCbCr 4:2:2 CSC Coefficient3 Register
(HW_LCDIF_CSC_COEFF3)
RGB to YCbCr 4:2:2 CSC Coefficient4 Register
(HW_LCDIF_CSC_COEFF4)
RGB to YCbCr 4:2:2 CSC Offset Register
(HW_LCDIF_CSC_OFFSET)
RGB to YCbCr 4:2:2 CSC Limit Register
(HW_LCDIF_CSC_LIMIT)
LCD Interface Data Register (HW_LCDIF_DATA)
Bus Master Error Status Register
(HW_LCDIF_BM_ERROR_STAT)
CRC Status Register (HW_LCDIF_CRC_STAT)
LCD Interface Status Register (HW_LCDIF_STAT)
LCD Interface Version Register (HW_LCDIF_VERSION)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LCDIF memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Chapter 33 LCD Interface (LCDIF)
R
R
00FF_00FFh
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0080_0010h
0000_0000h
0000_0000h
0000_0000h
9500_0000h
0400_0000h
33.4.10/2095
33.4.11/2096
33.4.12/2097
33.4.13/2098
33.4.14/2098
33.4.15/2099
33.4.16/2100
33.4.17/2101
33.4.18/2102
33.4.19/2103
33.4.20/2104
33.4.21/2105
33.4.22/2106
33.4.23/2107
33.4.24/2107
33.4.25/2109
33.4.26/2109
33.4.27/2110
33.4.28/2110
33.4.29/2112
33.4.8/2093
33.4.9/2094
Section/
page
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