MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1485

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

22.8.1 Real-Time Clock Control Register (HW_RTC_CTRL)
HW_RTC_CTRL is the control register for the RTC.
HW_RTC_CTRL: 0x000
HW_RTC_CTRL_SET: 0x004
HW_RTC_CTRL_CLR: 0x008
HW_RTC_CTRL_TOG: 0x00C
The contents of this register control the operation of the RTC portions implemented as an
APBX peripheral running in the APBX clock domain. These functions only operate when
the chip is in its full power up state.
EXAMPLE
Address:
Freescale Semiconductor, Inc.
Reset
Reset
its status bit
Bit
Bit
CLKGATE
W
W
R
R
SFTRST
Field
31
30
31
15
1
0
HW_RTC_CTRL
30
14
1
0
HW_RTC_CTRL_CLR(BM_RTC_CTRL_ALARM_IRQ); // reset the alarm interrupt by clearing
HW_RTC_CTRL_CLR(BM_RTC_CTRL_SFTRST);
HW_RTC_CTRL_CLR(BM_RTC_CTRL_CLKGATE); // enable clocks within the RTC
1= Hold real time clock digital side in soft reset state. This bit has no effect on the RTC analog.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. This
bit has no effect on RTC analog.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
8005_6000h base + 0h offset = 8005_6000h
RSVD0[15:7]
HW_RTC_CTRL field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits
24
0
0
8
Description
RSVD0[29:16]
23
0
0
7
// remove the soft reset condition
22
0
0
6
21
0
5
1
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1485
16
0
0
0