MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2197

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Address:
Re-
34.4.54 PXP Overlay 7 Size (HW_PXP_OL7SIZE)
This register contains buffer size/location information for the Overlay 7 input buffer.
This register contains information about Overlay 7 indicating the size of the overlay (in
NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In
16 pixel block size mode, only the low 7 bits of each field can be used and the most
significant bit must be set to 0.
EXAMPLE
HW_PXP_OLnSIZE_WR(7,0x10000401); // 32x8 overlay at offset +128+0
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
HEIGHT
XBASE
YBASE
WIDTH
ADDR
31 24
23 16
Field
31 0
Field
15 8
7 0
30
30
0
0
29
29
0
0
HW_PXP_OL7
HW_PXP_OL7SIZE
XBASE
28
28
0
0
Address pointer for the overlay 7 buffer. The address MUST be word-aligned for proper PXP operation.
This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output
frame buffer.
This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output
frame buffer.
Indicates number of horizontal NxN blocks in the image (non-rotated).
Indicates the number of vertical NxN blocks in the image (non-rotated).
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
8002_A000h base + 3C0h offset = 8002_A3C0h
23
23
0
0
HW_PXP_OL7SIZE field descriptions
8002_A000h base + 3D0h offset = 8002_A3D0h
22
22
0
0
HW_PXP_OL7 field descriptions
21
21
0
0
YBASE
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
ADDR
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
WIDTH
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
Chapter 34 Pixel Pipeline (PXP)
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
HEIGHT
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
2197
0
0
0
0