MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1141

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.35 DRAM Control Register 37 (HW_DRAM_CTL37)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
TRAS_LOCKOUT
Bit
W
R
CASLAT_LIN_
FAST_WRITE
OBSOLETE
31
0
RSVD1
RSVD4
31 28
27 24
GATE
Field
15 8
Field
7 1
RSVD4
16
30
0
0
29
0
HW_DRAM_CTL37
28
0
CASLAT_LIN_
Allow the controller to execute auto pre-charge cmds before TRAS_MIN expires.
Defines the tRAS lockout setting for the DRAM device. tRAS lockout allows the EMI to execute auto pre-charge
commands before the tras_min parameter has expired.
'b0 = tRAS lockout not supported by memory device.
'b1 = tRAS lockout supported by memory device.
Always write zeroes to this field.
Always write zeroes to this field.
Define when write cmds are issued to DRAM devices.
Controls when the write commands are issued to the DRAM devices.
'b0 = The EMI will issue a write command to the DRAM devices when it has received enough data for one
DRAM burst. In this mode, write data can be sent in any cycle relative to the write command. This mode
also allows for multi-word write command data to arrive in non-sequential cycles.
'b1 = The EMI will issue a write command to the DRAM devices after the first word of the write data is
received by the EMI. The first word can be sent at any time relative to the write command. In this mode,
multi-word write command data must be available to the EMI in sequential cycles.
Always write zeroes to this field.
Adjusts data capture gate open by half cycles.
Adjusts the data capture gate open time by 1/2 cycle increments. This parameter is programmed differently
than caslat_lin when there are fixed offsets in the flight path between the memories and the EMI for clock
gating. When caslat_lin_gate is a larger value than caslat_lin, the data capture window will become shorter.
A caslat_lin_gate value smaller than caslat_lin may have no effect on the data capture window, depending
on the fixed offsets in the ASIC and the board.
For optimal synthesis behavior, the ODT path for a CAS latency of three is clocked at a 200 MHz clock
regardless of configured maximum speed.
27
0
26
GATE
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL36 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL37 field descriptions
800E_0000h base + 94h offset = 800E_0094h
RSVD3
22
0
21
0
20
0
19
0
CASLAT_LIN
18
0
17
0
16
0
15
0
Description
Description
14
0
RSVD2
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
CASLAT
0
9
0
8
0
7
RSVD1
0
6
0
5
0
4
3
0
WRLAT
0
2
0
1
1141
0
0