MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1467

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
BUS_ERR_IRQ_
LATENCY_IRQ_
TRAP_ENABLE
BUS_ERR_IRQ
TRAP_IRQ_EN
LATENCY_IRQ
LATENCY_
TRAP_IRQ
TRAP_IN_
READ_EN
IRQ_MID
ENABLE
RANGE
RSVD1
23 16
15 13
SNAP
Field
RUN
CLR
EN
EN
12
11
10
9
8
7
6
5
4
3
2
1
0
This field contains the master ID and sub ID associated with the interrupt. If multiple IRQs, it is the ID
associated the first IRQ transaction, and will not update until the IRQ being cleared.
Always set this bit field to zero.
This bit is set if there is error on any AXI transaction and the BUS_ERR_IRQ_EN bit is set.
This status bit is set if maximum latency is above the value defined in the latency threshold register and the
LATENCY_ENABLE bit is set. Writing a one to its SCT clear address to clear it.
This status bit is set to indicate that an address trap occurs. This bit is cleared by software by writing a one
to its SCT clear address. This bit is set if axi address is within the pre-configured address range and the trap
function is enabled with TRAP_ENABLE bit.
Enables the PerfMon AXI BUS ERROR IRQ. When an error occurs and this bit is set, an interrupt is sent to
the ARM core.
Enables the PerfMon Latency threshold IRQ. When an error occurs and this bit is set, an interrupt is sent
to the ARM core.
Enables the PerfMon Address Trap IRQ. When an trap occurs and this bit is set, an interrupt is sent to the
ARM core.
Enables the PerfMon AXI latency threshold functions. When a transfer latency larger than the threshold and
this bit is set, the LATENCY_IRQ status bit will be set.
Determines whether the debug trap function causes a match when the master address is inside (low-address
<= current-address <= high-address) the specified range.
0 = The trap occurs when the master address falls outside of the range.
1 = The check is inside the range.
Enables the PerfMon AXI address trap functions. When a trap occurs and this bit is set, the TRAP_IRQ
status bit will be set.
Set this bit to One to monitor all Read transactions, set to zero to monitor all Write transactions.
0 = performance monitoring on all WRITE activities.
1 = performance monitoring on all READ activities.
Set this bit to clear all the PerfMon's statistics registers. This bit will be reset to 0 once the clear process is
done.
Set this bit to snap shot PerfMon's statistics registers into the shadow registers for reads. PerfMon will
continue collecting and updating statistics registers. This bit will be reset to 0 once the snapshot processing
is done.
Set this bit to one to enable the PerfMon operation.
0x0
0x1
HW_PERFMON_CTRL field descriptions (continued)
HALT — No PerfMon command in progress.
RUN — Process Performance monitoring.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Chapter 21 Performance Monitor (PERFMON)
1467