MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1422

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Operation
20.2 Operation
The APB interface of the OCOTP provides two functions:
The OTP is divided into 32-bit words (40 in total). All of the 40 words are memory-mapped
to APBH addresses (for reads only). Writes require the use of HW_OCOTP_CTRL_ADDR.
The high-level OTP allocation for i.MX28 is shown below.
1422
• Programmer-model access to registers (see
• Restricted 32-bit word write/program access to the 1.25 Kbit OTP.
These operations require a bank opening sequence through
HW_OCOTP_CTRL_RD_BANK_OPEN.
Figure 20-1. On-Chip OTP (OCOTP) Controller Block Diagram
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
APB Interface
HW/SW Capability, LOCK and
OTP Controller/State Machine
/
HW_OCOTP_DATA
HW_OCOTP_CTRL
ROM Shadow Regs
_
OCOTP
Programmable Registers
HW Capability Bus
Crypto Keys
Interface
Test /Pin
Blocks
DCP
To
All
Freescale Semiconductor, Inc.
for register details).

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