MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 355

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
8000_43C0
8000_43D0
8000_44C0
8000_44D0
8000_43A0
8000_43B0
8000_43E0
8000_43F0
8000_4400
8000_4410
8000_4420
8000_4430
8000_4440
8000_4450
8000_4460
8000_4470
8000_4480
8000_4490
8000_44A0
8000_44B0
8000_44E0
Absolute
address
(hex)
APBH DMA Channel 6 Current Command Address Register
(HW_APBH_CH6_CURCMDAR)
APBH DMA Channel 6 Next Command Address Register
(HW_APBH_CH6_NXTCMDAR)
APBH DMA Channel 6 Command Register
(HW_APBH_CH6_CMD)
APBH DMA Channel 6 Buffer Address Register
(HW_APBH_CH6_BAR)
APBH DMA Channel 6 Semaphore Register
(HW_APBH_CH6_SEMA)
AHB to APBH DMA Channel 6 Debug Information
(HW_APBH_CH6_DEBUG1)
AHB to APBH DMA Channel 6 Debug Information
(HW_APBH_CH6_DEBUG2)
APBH DMA Channel 7 Current Command Address Register
(HW_APBH_CH7_CURCMDAR)
APBH DMA Channel 7 Next Command Address Register
(HW_APBH_CH7_NXTCMDAR)
APBH DMA Channel 7 Command Register
(HW_APBH_CH7_CMD)
APBH DMA Channel 7 Buffer Address Register
(HW_APBH_CH7_BAR)
APBH DMA Channel 7 Semaphore Register
(HW_APBH_CH7_SEMA)
AHB to APBH DMA Channel 7 Debug Information
(HW_APBH_CH7_DEBUG1)
AHB to APBH DMA Channel 7 Debug Information
(HW_APBH_CH7_DEBUG2)
APBH DMA Channel 8 Current Command Address Register
(HW_APBH_CH8_CURCMDAR)
APBH DMA Channel 8 Next Command Address Register
(HW_APBH_CH8_NXTCMDAR)
APBH DMA Channel 8 Command Register
(HW_APBH_CH8_CMD)
APBH DMA Channel 8 Buffer Address Register
(HW_APBH_CH8_BAR)
APBH DMA Channel 8 Semaphore Register
(HW_APBH_CH8_SEMA)
AHB to APBH DMA Channel 8 Debug Information
(HW_APBH_CH8_DEBUG1)
AHB to APBH DMA Channel 8 Debug Information
(HW_APBH_CH8_DEBUG2)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH memory map (continued)
Register name
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
00A0_0000h
00A0_0000h
00A0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
6.5.50/420
6.5.51/420
6.5.52/421
6.5.53/423
6.5.54/423
6.5.55/424
6.5.56/427
6.5.57/427
6.5.58/428
6.5.59/428
6.5.60/430
6.5.61/431
6.5.62/432
6.5.63/434
6.5.64/435
6.5.65/435
6.5.66/436
6.5.67/438
6.5.68/439
6.5.69/440
6.5.70/442
Section/
page
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