MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1670

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1670
CNTL_FRM_ENA
PAUSE_FWD
RMII_MODE
CRC_FWD
MII_MODE
RMII_10T
RSRVD0
RSRVD0
RSRVD0
RSRVD0
PAD_EN
BC_REJ
PROM
Field
FCE
DRT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MAC Control Frame Enable. When set to 1, MAC Control frames with any Opcode other than 0x01 (Pause
Frame) are silently discarded. When set to 0 (Reset value), MAC Control frames with any Opcode other
than 0x01 are accepted and forwarded to the Client interface.
Terminate / Forward Received CRC. If cleared (Reset value 0) the CRC field of received frames is transmitted
to the user application. If set to 1 the CRC field is stripped from the frame.
Note: If padding function is enabled (Bit PAD_EN set to 1), CRC_FWD is ignored and the CRC field is
checked and always terminated and removed.
Terminate / Forward Pause Frames. If enabled (Set to 1) pause frames are forwarded to the user application.
In normal mode (Set to reset value 0) pause frames are terminated and discarded in the MAC.
Enable / Disable Frame Padding Remove on receive. If enabled (Set to 1) padding is removed from received
frames. If disabled (set to reset value 0) no padding is removed on receive by the MAC.
Reserved bits. Write as 0.
Reserved bits. Write as 0.
RMII 10-Base T. Enables 10Mbps mode of the RMII. When set to 1, the controller signal set_10 is set to 1,
when set to 0 set_10 is set to 0.
RMII Mode Enable. Indicates, when ECR(ETH_SPEED) is set to 0, if the MAC is in RMII or MII.
0 MAC configured for MII mode.
1 MAC configured for RMII operation.
When set to 1, the controller signal ena_rmii is set to 1, when set to 0, ena_rmii is set to 0.
Reserved bits. Write as 0.
Reserved bits. Write as 0.
Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
transmitter will stop transmitting data frames for a given duration.
Broadcast frame reject. If asserted, frames with DA (destination address) equals 0xFFFFFFFFFFFF are
rejected unless the PROM bit is set. If both BC_REJ and PROM equals 1, frames with broadcast DA are
accepted and the M (MISS) is set in the receive buffer descriptor.
Promiscuous mode. All frames are accepted regardless of address matching.
Media independent interface mode. Should always be set to 1, setting MII_MODE to 0 has no effect.
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half
duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
HW_ENET_MAC_RCR field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.