MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1027

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.3.2 DCP Status Register (HW_DCP_STAT)
The DCP Interrupt Status register provides channel interrupt status information.
HW_DCP_STAT: 0x010
HW_DCP_STAT_SET: 0x014
HW_DCP_STAT_CLR: 0x018
HW_DCP_STAT_TOG: 0x01C
This register provides status feedback indicating the channel currently performing an
operation and which channels have pending operations.
EXAMPLE
Address:
Freescale Semiconductor, Inc.
Reset
INTERRUPT_
INTERRUPT_
RSVD_CSC_
SWITCHING
CONTEXT_
CHANNEL_
ENABLE_
Bit
W
ENABLE
ENABLE
R
RSVD0
Field
20 9
7 0
21
8
31
0
RSVD2
HW_DCP_STAT
30
0
Enable automatic context switching for the channels. Software should set this bit if more than one channel
is doing hashing or cipher operations that require context to be saved (for instance, when CBC mode is
enabled). By disabling context switching, software can save the 208 bytes used for the context buffer.
Reserved, always set to zero.
Reserved, always set to zero.
Per-channel interrupt enable bit. When set, the channel's interrupt will get routed to the interrupt controller.
Channel 0 is routed to the dcp_vmi_irq signal and the other channels are combined (along with the CRC
interrupt) into the dcp_irq signal.
0x01
0x02
0x04
0x08
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
CH0 —
CH1 —
CH2 —
CH3 —
HW_DCP_CTRL field descriptions (continued)
READY
OTP_
KEY_
28
1
8002_8000h base + 10h offset = 8002_8010h
27
0
CUR_CHANNEL
26
0
25
0
24
0
Description
23
0
22
0
21
0
READY_CHANNELS
Chapter 13 Data Co-Processor (DCP)
20
0
19
0
18
0
17
0
1027
16
0