MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1185

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
14.8.89 DRAM Control Register 94 (HW_DRAM_CTL94)
This is a DRAM configuration register.
Address:
Re-
14.8.90 DRAM Control Register 95 (HW_DRAM_CTL95)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
DLL_CTRL_
REG_1_3
31
31
0
0
Field
Field
31 0
30
30
0
0
29
29
0
0
HW_DRAM_CTL94
HW_DRAM_CTL95
28
28
0
0
Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is
recommended to keep this field small (around 0x4) to keep the steps gradual.
All other bits undefined.
Holds the clk_wr settings and the Dll increment value for data slice 3.
There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus.
Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X
[28] = 'b1) Each increment of this field represents 1/128th of a clock cycle.
Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value
is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle.
Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is
recommended to keep this field small (around 0x4) to keep the steps gradual.
All other bits undefined.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
HW_DRAM_CTL93 field descriptions (continued)
24
24
0
0
23
23
0
0
HW_DRAM_CTL94 field descriptions
800E_0000h base + 178h offset = 800E_0178h
800E_0000h base + 17Ch offset = 800E_017Ch
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
DLL_CTRL_REG_1_3
DLL_OBS_REG_0_0
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
Chapter 14 External Memory Interface (EMI)
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1185
0
0
0
0

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