MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2209

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 35 Serial Audio Interface (SAIF)
For 17-bit to 24-bit operation, samples are placed in individual FIFO entries, are right
justified (LSB in bit 0), and the unused MSBs are zero-filled.
The first sample pushed to the FIFO at the start of operation is always a left sample, followed
by a right, and so on. If 4 or 6 channel pairs are enabled, sample pairs are grouped when
pushed to the FIFO with all left samples first, followed by all right samples (for example,
front left, surround left, then center, followed by front right, surround right then LFE, and
so on). As long as the BITCLK and LRCLK pins continue to transition, data is collected
within the FIFO. If the FIFO ever overflows or underflows, an interrupt occurs. At this
point, the system software should shut down the SAIF, clear the FIFO(s), and then cleanly
resume operation because there is not a way to determine left from right PCM channel data
within the FIFO after this point. If the FIFO does overflow, any PCM value that is pushed
to the full FIFO is discarded, not allowing the top entry to be overwritten. If the FIFO
underflows, the read of the empty FIFO returns all zeros.
When the run bit is cleared at the end of operation, all PCM data corresponding to one
sample collection (either two, four, or six channel pairs) that are currently being serially
received are allowed to complete and are stored to the FIFO before operation ceases.
Software can be used to empty the FIFO if the DMA is not used, either by responding to
an interrupt that is issued whenever an empty FIFO entry exists, or by polling a FIFO status
bit.
35.2.4 DMA Interface
Both SAIFs on the device are assigned to APBX DMA channels. See
AHB-to-APBX Bridge
Overview
for the DMA channel assignments.
Once the DMA channel and SAIF are programmed (except for the RUN bit), operation can
be initiated either by setting the SAIF's RUN bit or by signaling a kick from the DMA
channel.
The HW_SAIF_CTRL_DMAWAIT_COUNT bit field can be programmed to wait 0 to 31
APBX clock cycles between each DMA request. This feature acts as a throttle on the
bandwidth required by the SAIF to allow delays such that DMA requests from other modules
can be serviced by the DMA controller.
35.2.5 PCM Data FIFO
The SAIF contains three 4-entry by 32-bit wide FIFOs. These FIFOs serve as a buffer to
ensure data is not corrupted if the DMA cannot service the SAIF before the next sample or
sample pair is processed by the SAIF. Access to the FIFOs is achieved through read/writes
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
2209