MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1631

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

The backoff time is represented by an integer multiple of slot times (1 slot is equal to a
512-bit time period). The number of delay slot times, before the nth retransmission attempt,
is chosen as a uniformly distributed random integer in the range:
For example, after the first collision, the backoff period (in slot time) is 0 or 1, if a collision
occurs on the 1st retransmission, the backoff period (in slot time) is 0, 1, 2 or 3 and so on.
The maximum backoff time (in 512-Bit time slots) is limited by N set to 10 as specified in
the IEEE 802.3 Standard.
If a collision occurs after 16 consecutive retransmissions, the Core reports an excessive
collision condition (Interrupt bit RL and transmit status bit tx_ts_stat(2)) and discards the
current packet from the FIFO.
In networks violating the standard requirements, a collision may occur after the transmission
of first 64 bytes. In this case, the Core stops the current packet transmission and discards
the rest of the packet from the transmit FIFO. The Core resumes transmission with the next
packet available in the Core transmit FIFO.
26.3.9 Full Duplex Flow Control Operation
26.3.9.1 Overview
Three conditions are handled by the Core's Flow Control engine:
Freescale Semiconductor, Inc.
• 0 < r < 2^k
• k = min(n, N) where n is the number of retransmissions and N = 10
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 26-14. Packet Re-Transmit Overview
Buffer Control
64x5 Retransmit
Retransmit
Buffer
rden
Core FIFO
Discard
Frame
Back off Period
MAC Transmit Datapath
MAC Transmit
Control
LFSR
Core Tx Engine
Chapter 26 Ethernet Controller (ENET)
col
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