MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2011

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
RSVD0
SLOM
VBPS
SDIS
Field
14 6
SRT
1 0
CM
ES
15
5
4
3
2
Short Reset Time.
Reserved
Vbus Power Select
0 = Output is 0.
1 = Output is 1.
This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named
to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip
source in systems when both are available.
Stream Disable Mode.
0 = Inactive (default).
1 = Active.
In Device Mode:
Setting to a 1 disables double priming on both RX and TX for low bandwidth systems. This mode, when
enabled, ensures that the RX and TX buffers are sufficient to contain an entire packet, so that the usual
double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems.
Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream
disable is active.
In Host Mode:
Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems
where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has
the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significative when stream disable is active. See
TXFILLTUNING and TXTTFILLTUNING to characterize the adjustments needed for the scheduler when
using this feature.
Note: The use of this feature substantially limits of the overall USB performance that can be achieved.
Setup Lockout Mode.
In device mode, this bit controls behavior of the setup lock mechanism.
0 = Setup Lockouts On (default).
1 = Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD).
Endian Select.
This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture.
The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within
the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.
0 = Little Endian (default): First byte referenced in least significant byte of 32-bit word.
1 = Big Endian: First byte referenced in most significant byte of 32-bit word.
Controller Mode.
HW_USBCTRL_USBMODE field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
2011