MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1585

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 25 Controller Area Network (FlexCAN)
This register has two 8-bit fields which reflect the value of the transmit error counter
(tx_err_counter field) and receive error counter (rx_err_counter field). The rules for
increasing and decreasing these counters are described in the CAN protocol and are
completely implemented in the FlexCAN module. Both counters are read only except in
freeze mode, where they can be written by the ARM. Writing to the error counter register
while in freeze mode is an indirect operation. The data is first written to an auxiliary register,
and then an internal request/acknowledge procedure across clock domains is executed. All
this is transparent to the user, except for the fact that the data takes some time to actually
be written to the register. If desired, software can poll the register to discover when the data
was actually written. FlexCAN responds to any bus state as described in the protocol, for
example, by transmitting an error active or error passive flag, delaying its transmission start
time (error passive), and avoiding any influence on the bus when in the bus-off state. The
following are the basic rules for FlexCAN bus state transitions: If the value of tx_err_counter
or rx_err_counter increases to exceed 127, the FLT_CONF field in the error and status
register is updated to reflect error passive state. If the FlexCAN state is error passive, and
either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while
the other already satisfies this condition, the FLT_CONF field in the error and status register
is updated to reflect error active state. If the value of tx_err_counter increases to be greater
than 255, the FLT_CONF field in the error and status register is updated to reflect the bus-off
state, and an interrupt is issued. The value of tx_err_counter is then reset to zero. If FlexCAN
is in the bus-off state, then tx_err_counter is cascaded together with another internal counter
to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
tx_err_counter is reset to zero and counts in a manner where the internal counter counts 11
such bits and then wraps around while incrementing the tx_err_counter. when tx_err_counter
reaches the value of 128, the FLT_CONF field in the error and status register is updated to
be error active and both error counters are reset to zero. at any instance of dominant bit
following a stream of less than 11 consecutive recessive bits, the internal counter resets
itself to zero without affecting the tx_err_counter value. If during system start-up, only one
node is operating, then its tx_err_counter increases in each message it is trying to transmit,
as a result of acknowledge errors (indicated by the ACK_ERR bit in the error and status
register). After the transition to error passive state, the tx_err_counter does not increment
anymore by acknowledge errors. Therefore the device never goes to the bus-off state. If the
rx_err_counter increases to a value greater than 127, it is not incremented further, even if
more errors are detected while being a receiver. At the next successful message reception,
the counter is set to a value between 119 and 127 to resume to error active state.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1585