MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 108

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

i.MX28 Product Features
The APB DMA mode still exists for backward compatibility, but is not recommended for
driving displays larger than QVGA (320 × 240).
See
1.3.19.2 Pixel Processing Pipeline (PXP)
The PXP performs all necessary post display frame pre-processing in hardware with minimal
CPU overhead. The PXP operation and features can be described as follows:
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• ITU-R/BT.656 compliant D1 digital video output mode with on-the-fly RGB to YCbCr
• Support for a wide variety of input and output formats that allows for conversion between
• The PXP can be programmed to operate in either 8 × 8 or 16 × 16 block modes. When
• The background image (for example, decoded video frames) is read from an external
• The scaled RGB image (in the internal S0 buffer) can be blended with up to eight
color-space-conversion. This output mode is suitable for driving the external
TV-Encoder.
input and output (for example, RGB565 input to RGB888 output). Also support for
packed byte formats.
LCD Interface (LCDIF) Overview
using 32-bit memories with the EMI, 16 ×16 block mode is recommended to allow for
efficient memory access. Because the PXP accesses the blocks by requesting a line of
block, a 16-pixel fetch (one line of a block) will make full use of a 16-byte burst on the
EMI.
memory (single-plane YUV, dual-plane Y/UV and three plane Y/U/V inter-leaved
source buffer formats are supported) into the internal buffers as either 8 × 8 or 16 ×16
pixel blocks. These buffers are then fed into a color-space converter (for example, YUV
to RGB) followed by the scaling engine which utilizes an advanced bi-linear weighted
scaling algorithm. The scaling operation is defined in terms of the output image (through
programmable offsets and cropping registers). The output of the scaler is fed into yet
another internal buffer called S0. If the background image is already in the RGB
color-space, it is assumed to be scaled appropriately for the required output format and
can thus be read directly into the internal S0 buffer. In order to maintain the efficient
use of an external memory, only the relevant (visible) portion of the background image
is fetched.
programmable overlays. The co-ordinates of the overlays can once again be described
in terms of the resultant output image. Each overlay can have either a global
programmable opacity or a per-pixel resolution if constructed with RGB color-space.
In addition to this, each overlay can have a relative priority level such that when
constructing the output image, the PXP only fetches the visible overlay in the current
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
for more information.
Freescale Semiconductor, Inc.