MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1573

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Exiting Freeze Mode is done in one of the following ways:
Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by waiting for
11 consecutive recessive bits.
25.4.11.2 Module Disable Mode
This low power mode is entered when the MDIS bit in the MCR Register is asserted. If the
module is disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM
sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit. If the module is disabled
during transmission or reception, FlexCAN does the following:
The Bus Interface Unit continues to operate, enabling the ARM to access memory mapped
registers, except the Free Running Timer, the Error Counter Register and the Message
Buffers, which cannot be accessed when the module is in Disable Mode. Exiting from this
mode is done by negating the MDIS bit, which will resume the clocks and negate the
LPM_ACK bit.
25.4.11.3 Stop Mode
This is a system low power mode in which all i.MX28 clocks are stopped for maximum
power savings. If FlexCAN receives the global Stop Mode request (through ipg_stop) during
Freeze Mode, it sets the LPM_ACK bit, negates the FRZ_ACK bit and then sends a Stop
Acknowledge signal to the ARM, in order to shut down the clocks globally. If Stop Mode
is requested during transmission or reception, FlexCAN does the following:
Freescale Semiconductor, Inc.
• ARM negates the FRZ bit in the MCR Register
• The MCU is removed from Debug Mode (negating ipg_debug) and/or the HALT bit
• Waits to be in either Idle or Bus Off state, or otherwise waits for the third bit of
• Waits for all internal activities like arbitration, matching, move-in and move-out to
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM sub-modules
• Sets the NOT_RDY and LPM_ACK bits in MCR
is negated
Intermission and then checks it to be recessive
finish
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 25 Controller Area Network (FlexCAN)
1573