MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1944

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
30.4.2 UART Transmit DMA Control Register (HW_UARTAPP_CTRL1)
The UART Transmit DMA Control Register contains the dynamic information associated
with the transmit command.
HW_UARTAPP_CTRL1: 0x010
HW_UARTAPP_CTRL1_SET: 0x014
HW_UARTAPP_CTRL1_CLR: 0x018
HW_UARTAPP_CTRL1_TOG: 0x01C
This register contains the main DMA controls for Transmitting data.
1944
Reset
RXTO_ENABLE
XFER_COUNT
RX_SOURCE
RXTIMEOUT
CLKGATE
Bit
W
SFTRST
R
26 16
Field
RUN
15 0
31
30
29
28
27
15
0
14
0
Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset
state.
Set this bit zero for normal operation. Setting this bit to one (default), gates all of the block level clocks off
for miniminizing AC energy consumption.
Tell the UART to execute the RX DMA Command. The UART will clear this bit at the end of receive execution.
Source of Receive Data. If this bit is set to 1, the status register will be the source of the DMA, otherwise
RX data will be the source.
RXTIMEOUT Enable: If this bit is set to 0, the RX timeout will not affect receive DMA operation. If this bit is
set to 1, a receive timeout will cause the receive DMA logic to terminate.
Receive Timeout Counter Value: number of 8-bit-time to wait before asserting timeout on the RX input. If
the RXFIFO is not empty and the RX input is idle, then the watchdog counter will decrement each bit-time.
Note 7-bit-time is added to the programmed value, so a value of zero will set the counter to 7-bit-time, a
value of 0x1 gives 15-bit-time and so on. Also note that the counter is reloaded at the end of each frame,
so if the frame is 10 bits long and the timeout counter value is zero, then timeout will occur (when FIFO is
not empty) even if the RX input is not idle. The default value is 0x3 (31 bit-time).
Number of bytes to receive. This must be a multiple of 4.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_UARTAPP_CTRL0 field descriptions
11
0
10
0
0
9
XFER_COUNT
0
8
Description
0
7
0
6
5
0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
0
1
0
0