MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2046

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
2046
ENAUTOCLR_PHY_PWD
ENIRQRESUMEDETECT
ENAUTOCLR_CLKGATE
ENAUTO_PWRON_PLL
ENDPDMCHG_WKUP
ENVBUSCHG_WKUP
RESUMEIRQSTICKY
ENIRQDEVPLUGIN
DATA_ON_LRADC
ENIDCHG_WKUP
DEVPLUGIN_IRQ
FSDLL_RST_EN
ENUTMILEVEL3
ENUTMILEVEL2
ENIRQWAKEUP
ENAUTOCLR_
USBCLKGATE
WAKEUP_IRQ
RESUME_IRQ
Field
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBPHY_CTRL field descriptions (continued)
Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in
HW_DIGCTL_CTRL if there is wakeup event on USB0/USB1 while USB0/USB1 is suspended.
This should be enabled if needs to support auto wakeup without S/W's interaction.
Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
Enables the feature to wakeup USB if ID is toggled when USB is suspended.
Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended. This bit is
enabled by default.
Enables the feature to auto-clear the PWD register bits in HW_USBPHY_PWD if there is wakeup
event while USB is suspended. This should be enabled if needs to support auto wakeup without
S/W's interaction.
Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is
suspended. This should be enabled if needs to support auto wakeup without S/W's interaction.
Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is
wakeup event if USB is suspended. This should be enabled if needs to support auto wakeup
without S/W's interaction.
Indicates that there is a wakeup event. Reset this bit by writing a 1 to the SCT clear address
space and not by a general write.
Enables interrupt for the wakeup events.
Enables UTMI+ Level3. This should be enabled if needs to support external FS Hub with LS
device connected
Enables UTMI+ Level2. This should be enabled if needs to support LS device
Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.
Indicates that the device is connected. Reset this bit by writing a 1 to the SCT clear address
space and not by a general write.
Enables interrupt for the detection of connectivity to the USB line.
Indicates that the host is sending a wake-up after suspend. This bit is also set on a reset during
suspend. Use this bit to wake up from suspend for either the resume or the reset case. Reset
this bit by writing a 1 to the SCT clear address space and not by a general write.
Enables interrupt for detection of a non-J state on the USB line. This should only be enabled
after the device has entered suspend mode.
Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it. Set to 0, RESUME_IRQ
only set during the wake-up period.
Description
Freescale Semiconductor, Inc.