MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 94

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

i.MX28 Product Features
An ARM926EJ-S CPU with 16K I$ & 32K D$ L1-caches and 128 Kbytes of on-chip SRAM
provides the processing power needed to support advanced features such as web browsing
and portable gaming (together with graphics and video processing hardware). Contact the
local Freescale representative for more information on the software board support packages
available for the i.MX28.
Execution always begins in on-chip ROM after reset, unless overridden by the debugger.
A number of devices are programmed only at initialization or application state change, such
as DC-DC converter voltages, clock generator settings and so on. Certain other devices
either operate in a crystal clock domain or have significant portions that operate in a crystal
clock domain, for example, ADC, PLLs and so on. These devices operate on a slower speed
asynchronous peripheral bus. Write posting in the ARM core, additional write post buffering
in the peripheral AHB, and set/clear operations at the device registers make these operations
efficient.
1.3.1 ARM9 CPU Subsystem
The on-chip RISC processor core is an ARM926EJ-S CPU. This CPU implements the ARM
v5TE instruction set architecture. This CPU has two instructions sets, a 32-bit instruction
set used in the ARM state and a 16-bit instruction set used in the Thumb state. The core
offers the choice of running in the ARM state or the Thumb state or a mix of the two states.
This enables optimization for both code density and performance. ARM studies indicate
that Thumb code is typically 65% the size of the equivalent ARM code, while providing
160% of the effective performance in a constrained memory bandwidth applications. The
ARM CPU is described in Overview.
The ARM RISC CPU is the central controller for the entire SOC, as shown in
1.3.2 System Buses
The i.MX28 uses buses based on ARM's Advanced Microcontroller Bus Architecture
(AMBA) for the on-chip peripherals. The AMBA2 specification
(http://www.arm.com/products/solutions/AMBA_Spec.html) outlines two bus types: AHB
and APB. The AMBA3 specification (http://www.arm.com/products/solutions/axi_Spec.html)
additionally outlines the AXI fabric. The three bus types are explained as follows:
94
• AHB1 Used for ARM instruction fetches
• AHB2 Used for ARM data load/stores
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
System
Buses.