MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1552

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Message Buffer Structure
25.3 Message Buffer Structure
The Message Buffer structure used by the FlexCAN module is represented in
Both Extended and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively)
used in the CAN specification (Version 2.0 Part B) are represented.
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• Listen-Only Mode:
• Loop-Back Mode:
• Module Disable Mode:
• Stop Mode:
The module enters this mode when the LOM bit in the Control Register is asserted. In
this mode, transmission is disabled, all error counters are frozen and the module operates
in a CAN Error Passive mode. Only messages acknowledged by another CAN station
will be received. If FlexCAN detects a message that has not been acknowledged, it will
flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the
message.
The module enters this mode when the LPB bit in the Control Register is asserted. In
this mode, FlexCAN performs an internal loop back that can be used for self test
operation. The bit stream output of the transmitter is internally fed back to the receiver
input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive
state (logic '1'). FlexCAN behaves as it normally does when transmitting and treats its
own transmitted message as a message received from a remote node. In this mode,
FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field
to ensure proper reception of its own message. Both transmit and receive interrupts are
generated.
This low power mode is entered when the MDIS bit in the MCR Register is asserted.
When disabled, the module shuts down the clocks to the CAN Protocol Interface and
Message Buffer Management sub-modules. Exit from this mode is done by negating
the MDIS bit in the MCR Register. See
This low power mode is entered when Stop Mode is requested at ARM chip level.When
in Stop Mode, the module puts itself in an inactive state and then informs the ARM
that the clocks can be shut down globally. Exit from this mode happens when the Stop
Mode request is removed or when activity is detected on the CAN bus and the Self
Wake Up mechanism is enabled. See
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Stop Mode
Module Disable Mode
for more information.
for more information.
Freescale Semiconductor, Inc.
Table
25-1.