MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1486

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
22.8.2 Real-Time Clock Status Register (HW_RTC_STAT)
HW_RTC_STAT is the status register for the RTC.
HW_RTC_STAT: 0x010
HW_RTC_STAT_SET: 0x014
HW_RTC_STAT_CLR: 0x018
HW_RTC_STAT_TOG: 0x01C
This register reflects the current state of the RTC in terms of its enabled capabilities and
the state of the persistent registers.
EXAMPLE
1486
FORCE_UPDATE
ONEMSEC_IRQ_
ALARM_IRQ_EN
COPY2ANALOG
ONEMSEC_IRQ
WATCHDOGEN
SUPPRESS_
ALARM_IRQ
RSVD0
29 7
Field
EN
6
5
4
3
2
1
0
while(HW_RTC_STAT.STALE_REGS !=0)
{
Reserved, write only zeroes.
This bit is used for diagnostic purposes. 1= suppress the automatic copy that normally occurs to the analog
side, whenever a shadow register is written. 0= Normal operation. Use SCT writes to set, clear, or toggle.
This bit is how the software requests the update of the shadow registers from values in RTC analog. When
software sets this bit, all eight of the shadow registers are updated from the corresponding values in the
persistent registers in RTC analog. The state of this update operation is reflected on the STALEREGS bits
on the STAT register, which are set to all ones upon an update request and are cleared by hardware as the
update proceeds. Hardware clears this bit immediately after detecting it has been set. Software does not
need to clear. Software must NOT look to the state of this bit to determine the status of the update operation,
it must look to the STALEREG bits in the STAT register to determine when any given register has been
updated and/or when the update operation is complete. Notice that the default value of this bit is 1, so that
that a reset (either chip-wide or soft) always results in an update.
1= Enable Watchdog Timer to force chip wide resets. Use SCT writes to set, clear, or toggle.
1= one millisecond interrupt request status. Use SCT writes to clear this interrupt status bit.
1= Alarm Interrupt Status. Use SCT writes to clear this interrupt status bit.
1= Enable one millisecond interrupt. Use SCT writes to set, clear, or toggle.
1= Enable Alarm Interrupt. Use SCT writes to set, clear, or toggle.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_RTC_CTRL field descriptions (continued)
Description
Freescale Semiconductor, Inc.