MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1047

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Reset
ERROR_SETUP
ERROR_CODE
ERROR_DST
ERROR_SRC
PAGEFAULT
COMPLETE
MISMATCH
Bit
W
ERROR_
ERROR_
PACKET
R
RSVD0
HASH_
RSVD_
31 24
23 16
Field
15 7
TAG
6
5
4
3
2
1
0
15
0
14
0
Indicates the tag from the last completed packet in the command structure
Indicates additional error codes for some error conditions.
0x01
0x02
0x03
0x04
0x05
Reserved, always set to zero.
This bit indicates a page fault occurred while converting a virtual address to a physical address.. When an
error is detected, the channel's processing will stop until the error handled by software.
This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the
channel's processing will stop until the error handled by software.
This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the
channel's processing will stop until the error handled by software.
This bit indicates that a bus error occurs when reading the packet or payload or when writing status back
to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled
by software.
This bit indicates that the hardware detected an invalid programming configuration such as a buffer length
that is not a multiple of the natural data size for the operation. When an error is detected, the channel's
processing will stop until the error is handled by software.
The bit indicates that a hashing check operation mismatched for control packets that enable the
HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled
by software.
This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing
of the packet has completed. This was done so that software can verify that each packet completed properly
in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion
bit for the channel is effectively the channel interrupt status bit.
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0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
NEXT_CHAIN_IS_0 — Error signalled because the next pointer is 0x00000000
NO_CHAIN — Error signalled because the semaphore is nonzero and neither chain bit is set
CONTEXT_ERROR — Error signalled because an error was reported reading/writing the context
buffer
PAYLOAD_ERROR — Error signalled because an error was reported reading/writing the payload
INVALID_MODE — Error signalled because the control packet specifies an invalid mode select (for
instance, blit + hash)
12
0
HW_DCP_CH1STAT field descriptions
RSVD0
11
0
10
0
0
9
0
8
Description
0
7
0
6
5
0
Chapter 13 Data Co-Processor (DCP)
4
0
0
3
0
2
0
1
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