MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2224

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Operation
SPDIF data can be transmitted in one of two modes: 32-bit mode and 16-bit mode. Selection
between these modes is done with the WORD_LENGTH bit in the HW_SPDIF_CTR
register. In either case, data samples must be interleaved in main memory for proper behavior,
although in 32-bit mode, 32-bit words are interleaved and in 16-bit mode, 16-bit words are
interleaved.
2224
• When WORD_LENGTH = 0, 32-bit mode is enabled, and HW_SPDIF_DATA contains
• Alternately, when WORD_LENGTH = 1, 16-bit mode is enabled, and the
either the left or right data sample. Since the SPDIF frame allows for transmission of
only 24 bits, only the 24 MSBs stored in the HW_SPDIF_DATA register will be
transmitted.
HW_SPDIF_DATA register will contain one of each left AND right samples. The data
transmitted in the SPDIF frame will be these 16 MSBs with 8 zeros appended in the
LSB positions.
If the data supplied actually represents a lower resolution
analog-to-digital conversion, this information is not captured by
the SPDIF transmitter, which always reports a 24-bit sample-size.
Final Validity=0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SPDIF_DATA = 0
1
Figure 36-2. SPDIF Flow Chart
Final Validity=0
0
HW_SPDIF_FRAMECTRL_AUTO_MUTE
0
HW_SPDIF_FRAMECTRL_V_CONFIG
HW_SPDIF_CTRL_FIFO
_UNDERFLOW_IRQ
SPDIF Normal Operation
Note
0
1
FRAMECTRL_V
HW_SPDIF_DATA = LAST_VALUE
HW_SPDIF_
Final Validity=1
1
Underflow asserted after 4-frames
consecutive frames w/empty FIFO
0
1
Final Validity=1
Freescale Semiconductor, Inc.

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