MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 886

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
HW_CLKCTRL_FRAC0_TOG: 0x1BC
This register controls the 9-phase fractional clock dividers. The fractional clock frequencies
are a product of the values in these registers. NOTE: This register can only be addressed
by byte instructions. Addressing word or half-word are not allowed.
EXAMPLE
*((u8 *)(HW_CLKCTRL_FRAC0_ADDR + 1)) = 30;
Address:
886
Reset
Reset
CLKGATEIO0
CLKGATEIO1
IO0_STABLE
IO1_STABLE
Bit
Bit
IO0FRAC
W
W
R
R
29 24
Field
31
30
23
22
31
15
1
1
HW_CLKCTRL_FRAC0
30
14
0
0
IO0 Clock Gate. If set to 1, the IO0 fractional divider clock (reference PLL0 ref_io0) is off (power savings).
0: IO0 fractional divider clock is enabled.
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not
invert when the fractional divider is taken out of or placed into clock-gated state.
This field controls the IO0 clocks fractional divider. The resulting frequency shall be 480 * (18/IO0FRAC)
where IO0FRAC = 18-35.
IO1 Clock Gate. If set to 1, the IO1 fractional divider clock (reference PLL0 ref_io1) is off (power savings).
0: IO1 fractional divider clock is enabled.
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not
invert when the fractional divider is taken out of or placed into clock-gated state.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
1
1
HW_CLKCTRL_FRAC0 field descriptions
EMIFRAC
IO0FRAC
27
11
0
0
8004_0000h base + 1B0h offset = 8004_01B0h
26
10
0
0
25
1
1
9
24
0
0
8
Description
23
1
1
7
22
0
0
6
21
0
5
0
20
1
4
1
Freescale Semiconductor, Inc.
CPUFRAC
IO1FRAC
19
0
0
3
18
0
0
2
17
1
1
1
16
0
0
0