MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2132

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
When the IN_PLACE control bit is set to 1, the control logic will optimize the PXP's
operations to only process the blocks that match an overlay region since all other pixels
will be unmodified. This considerably reduces the processing time as well as the memory
bandwidth used.
In place rendering is enabled by setting the IN_PLACE bit in the HW_PXP_CTRL registers.
Note the following restrictions when rendering in place:
34.2.11 Interlaced Video Support
The PXP has some minimal ability to generate interlaced video content from a progressive
source. There two available options, based on the bandwidth requirements and how software
is managing video frames. The PXP can either interlace on the input side (by reading every
other line of input data) or on the output side (by writing the individual lines of video into
two separate fields). Generally, output interleaving should be used since it is the most
flexible mode (it allows scaling and full overlay support) and it only requires a single pass
of the PXP to generate two separate output fields. Input interleaving can be beneficial in
cases where the PXP is running at 60 fps, since it requires fewer fetches to produce the
output data.
The PXP will perform input interlacing when the INTERLACED_INPUT field is
programmed to either FIELD0 or FIELD1 (to select the desired field). When performing
output interlacing, the PXP will write field0 data to the OUTBUF pointer and the field1
data to the OUTBUF2 pointer. The OUTPUT_INTERLACING field of the HW_PXP_CTRL
register controls which of these fields (or both) are generated.
34.2.12 Queueing Frame Operations
The PXP supports a primitive ability to queue up one operation while the current operation
is running. This is enabled through the use of the HW_PXP_NEXT register. When this
register is written, it enables the PXP to reload its current register contents with the data
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• The source buffer is used as the destination buffer (RGBBUF is not used)
• Only RGB S0 images are supported (not YUV)
• The output RGB format must be programmed to the same value as the input RGB
format
Output interlacing AND 2-plane output modes are not supported
concurrently.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Note
Freescale Semiconductor, Inc.