MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 98

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

i.MX28 Product Features
Other boot modes are responsible for loading the application code from off-chip into the
on-chip RAM. It supports initial program loading from a number of sources:
At power-on time, the first instruction executed by the ARM core comes from this ROM.
The reset boot vector is located at 0xFFFF0000. The on-chip boot code includes a firmware
recovery mode. If the device fails to boot from NAND Flash, or hard drive, for example,
the device will attempt to boot from a PC host connected to its USB port.
The ROM boot loader can be restricted to boot only properly certified load packages. This
function is enabled by an OTP bit. Additional laser fuse bits select one of the 16 customer
keys, which are further modified by laser fuses. A polynomial LSFR is used to decrypt the
supplied boot package. A second polynomial computes an authentication code for the load
package. If the decrypted package does not compute the correct authentication code, then
the boot loader will enter recovery mode and attempt to boot from the USB device.
See
Memory Map Overview
indicate that nothing is mapped at that address. No accesses should be made to these
addresses because the results are indeterminate. The Decode Block column indicates the
decode group to which each peripheral belongs. Most peripherals reside on the APBH,
APBX and Axi0 (through AHB0).
1.3.4 On-Chip One-Time-Programmable (OCOTP) ROM
The device contains 1280 bits of One-Time-Programmable (OTP) ROM. The OTP is
segmented into five distinct physical banks. Each bank is further divided logically into eight
32-bit words. The OTP serves several functions:
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• NAND Flash devices
• SD2.0/MMC4.4, 4.3,4.2
• SPI from EEPROM devices or NOR Flash devices
• USB recovery mode
• I2C
• Housing of hardware and software capability bits (copied into shadow registers).
• Housing of Freescale operations and unique-ID fields.
• Housing the customer-programmable cryptography key.
• Four words for customer general use.
Boot Modes
for more information.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
shows the memory map as seen by the processor. Any blank entries
Freescale Semiconductor, Inc.