MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1733

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

In slave mode, the default I
slave address is programmable.
Data transfer with acknowledge is obligatory.
The clock is generated by the master, according to parameters set in the HW_I2C_TIMINGn
register. This register also provides programmable timing for capturing received data, as
well as for changing the transmitted data bit.
Freescale Semiconductor, Inc.
• When an address is sent, each device in the system compares the first seven bits after
• If they match, the device considers itself addressed by the master.
• The transmitter must release the I2C_SDA line during the acknowledge pulse.
• The receiver must then pull the data line low, so that it remains stable low during the
• A receiver that has been addressed is obliged to generate an acknowledge after each
• A slave device can terminate a transfer by withholding its acknowledgement.
a start condition with its address.
high period of the acknowledge clock pulse.
byte of data has been received.
SDA
SCL
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Condition
START
Figure 27-2. I
2
SLAVE Address and R /W
End of the
Slave Address
Search Engine
Processing
C write address is 86h, and its default read address is 87h. The
8 Bits
2
C Data and Clock Timing
Acknowledge
Signal
I
2
C Clock Held
Beginning of DMA
Transfer Engine
Processing
DATA
8 Bits
Acknowledge
Signal
Condition
STOP
Chapter 27 Inter IC (I2C)
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