MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1726

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Programmable Registers
26.4.110 ENET MAC Capture register 3 (HW_ENET_MAC_CAPT_REG_3)
Timer value latched when a rising edge occured on input pin evt_in(3).
Address:
Re-
26.4.111 ENET MAC IEEE1588 Interrupt register.
For each capture/compare event an interrupt can be generated. The interrupt is cleared by
writing a 1 to the corresponding bit
Note: The interrupt bits are set on event occurence. To clear an interrupt the corresponding
bit must be written with 1.
Address:
1726
set
Reset
Bit
W
R
CAPT_REG_2
CAPT_REG_3
Bit
31
W
0
R
Field
31 0
Field
31 0
30
0
31
0
29
0
HW_ENET_MAC_CCB_INT
0680h
HW_ENET_MAC_CAPT_REG_3 800F_0000h base + 64Ch offset = 800F_064Ch
28
0
30
0
(HW_ENET_MAC_CCB_INT)
Value of capture register 2
Value of capture register 3
27
0
26
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
HW_ENET_MAC_CAPT_REG_2 field descriptions
HW_ENET_MAC_CAPT_REG_3 field descriptions
0
24
0
28
0
23
0
22
0
27
0
21
0
800F_0000h base + 680h offset = 800F_
20
0
26
RSRVD0
0
19
0
18
25
0
0
CAPT_REG_3
17
0
16
24
0
0
15
0
Description
Description
23
14
0
0
13
0
22
12
0
0
11
0
21
0
10
0
0
9
20
0
0
8
Freescale Semiconductor, Inc.
0
7
19
0
0
6
0
5
18
0
0
4
3
0
17
0
0
2
0
1
16
0
0
0

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