MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1565

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

If the ARM writes the abort code before the transmission begins internally, then the write
operation is not blocked, therefore the MB is updated and no interrupt flag is set. In this
way the ARM just needs to read the abort code to make sure the active MB was deactivated.
Although the AEN bit is asserted and the ARM wrote the abort code, in this case the MB
is deactivated and not aborted, because the transmission did not start yet. One MB is only
aborted when the abort request is captured and kept pending until one of the previous
conditions are satisfied.
The abort procedure can be summarized as follows:
25.4.7 Message Buffer Deactivation
Deactivation is a mechanism provided to maintain data coherence when the ARM writes
to the Control and Status word of active MBs out of Freeze Mode. Any ARM write access
to the Control and Status word of a MB causes that MB to be excluded from the transmit
or receive processes during the current matching or arbitration round. The deactivation is
temporary, affecting only for the current match/arbitration round.
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs
to decide which MB to transmit or receive. If the ARM updates the MB in the middle of a
match or arbitration process, the data of that MB may no longer be coherent, therefore
deactivation of that MB is done.
Even with the coherence mechanism described above, writing to the Control and Status
word of active MBs when not in Freeze Mode may produce undesirable results. Examples
are:
Freescale Semiconductor, Inc.
• ARM writes 1001 into the code field of the C/S word
• ARM reads the CODE field and compares it to the value that was written
• If the CODE field that was read is different from the value that was written, the ARM
• Matching and arbitration are one-pass processes. If MBs are deactivated after they are
must read the corresponding IFLAG to check if the frame was transmitted or it is being
currently transmitted. If the corresponding IFLAG is set, the frame was transmitted. If
the corresponding IFLAG is reset, the ARM must wait for it to be set, and then the
ARM must read the CODE field to check if the MB was aborted (CODE=1001) or it
was transmitted (CODE=1000).
scanned, no re-evaluation is done to determine a new match/winner. If a Rx MB with
a matching ID is deactivated during the matching process after it was scanned, then
this MB is marked as invalid to receive the frame, and FlexCAN will keep looking for
another matching MB within the ones it has not scanned yet. If it can not find one, then
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 25 Controller Area Network (FlexCAN)
1565